The present invention relates generally to deposition and/or etching of layers of material on a partially fabricated integrated circuit. More specifically, it relates to deposition of diffusion barrier layers.
Generally, the industry of semiconductor manufacturing involves highly complex techniques for fabricating integrating circuits from semiconductor materials that are layered and patterned onto a substrate, such as silicon, by various process systems. For example, a first process system deposits a layer of material, while another process system etches a pattern in such deposited material.
Miniaturization of integrated circuit (IC) devices demands superior electrical properties from both dielectric and conductive materials used in the manufacturing of an integrated circuit. Traditionally used materials, such as aluminum as a conductor and silicon dioxide as an insulator no longer provide adequate electrical characteristics at the modern level of miniaturization. Therefore, the manufacturers of IC devices are now employing new dielectric materials with lower dielectric constant than silicon dioxide and are increasingly turning to copper as a conductor, due to its low resistivity. The low-k dielectric materials used in the IC device processing include carbon doped silicon dioxide, hydrogenated silicon oxycarbides (SiCOH), fluorine doped silicon dioxide, and organic-containing low-k dielectrics. These materials, due to their low dielectric constants, provide low parasitic capacitance and minimize the “crosstalk” between the interconnects in an integrated circuit. At the same time, they are often porous foam-like materials and are generally more easily damaged during the processing steps than silicon dioxide. The impact of high-energy ions during such processing steps as PVD (physical vapor deposition) often results in undesired effects in a highly porous dielectric.
FIGS. 1A and 1B are cross sectional views of a partially formed semiconductor device to illustrate a process that tends to damage highly porous dielectric materials. As shown, a first dielectric layer 102 has already been etched to form a recessed feature into which a conductive copper plug 116 has been formed. The trench and via into which the copper plug is formed is lined with a diffusion barrier layer 117. In a second dielectric layer 104 a trench 110 and a via 114 are formed. A diffusion barrier layer 106 is also formed over the dielectric layer 104. This barrier layer 106 is typically formed with a uniform thickness in both the trench 110 and via 114. That is, barrier portion 108 in the trench 110 has about a same thickness as barrier portion 112 in the via 114.
The barrier material 106 is removed from the bottom surface 112 of the via 114 along with any underlying oxidized copper so as to form a better connection to the conductive line 116 in a subsequent process step. Since the barrier material was deposited uniformly in the trench and the via, cleaning all of the barrier material from the via also results in etching into the dielectric material underneath the trench's barrier layer. FIG. 1A illustrates the partially formed device prior to removal of the barrier material 106 from the trench and via, while FIG. 1B shows the device after removal of the barrier material from the trench and via 114. As shown, although the bottom of the via 120 is cleaned sufficiently to expose the underlying copper material, the dielectric material within the bottom of the trench 118 is damaged during this etch process. As shown, damage is created within the dielectric material beneath the trench. Damage will tend to form in highly porous dielectric materials, such as ultra low k dielectric materials. This damage may lead to adverse effects, such as time dependent dielectric breakdown (TDDB) that then causes device failure.
Accordingly, it would be beneficial to provide improved apparatus and methods for facilitating etching of via features without damaging the dielectric material within trench features or other features of a semiconductor wafer.